The present invention relates to a complementary metal-oxide-semiconductor (CMOS) voltage regulator circuit for reducing digital signal noise in mixed mode integrated circuits. CMOS integrated circuits are currently used in many digital logic applications. These circuits are relatively fast and consume little power during the static or non-switching state.
FIG. 1 illustrates a circuit schematic of a basic CMOS inverter 10, the fundamental component of most CMOS logic circuits. Inverter 10 has an input node 12, an output node 14, a p-channel transistor 16, and an n-channel transistor 18. The transistors are connected to V.sub.DD (power) and GND (ground) as shown, and their gates are tied together as shown. In operation, application of a low potential at input node 12 causes n-channel transistor 18 to turn off and renders p-channel transistor 16 conductive, thereby coupling output 14 to V.sub.DD. Application of a high potential to input node 12 turns off p-channel transistor 16 and turns on n-channel 18, coupling output 14 to V.sub.SS.
When a CMOS device, such as inverter 10, is in a steady-state condition (not switching between output states), there is no current flow in the inverter from the power supply. If the inverter output switches from low to high, two components of current are drawn from V.sub.DD --an overlap current and a displacement current. The overlap current, which exists during the brief moment when both transistors are conducting, flows through both the pmos and nmos transistors to ground. The displacement current (i.e., C.sub.l *dV.sub.out /dt) flows through the pmos transistor only to charge the load capacitance (C.sub.l). At high switching frequencies, the displacement current is large. As it flows through parasitic resistances and inductances associated with the digital power grid, bonding pads and wires, package pins, etc., resulting in digital switching noise. If the digital V.sub.SS power supply line is connected to the substrate (common practice in p-well CMOS technology), the power supply switching noise due to current surges from charging and discharging of the loads at the gates is coupled directly into the n-substrate, which is shared by analog circuitry. The digital switching noise can be problematic to the operation of the analog circuitry, which can be fairly sensitive. In addition to CMOS static logic, other logic families such as dynamic logic, exhibit similar noise generation problems.
Prior attempts at a solution to the problem--including power supply filters, wide spacings and diffused guardbands between the analog and digital subsection, separate analog and digital supply lines, separate bonding pads and wires, as well as separate package pins--have proven unacceptable. These attempts resulted only in a reduction in the transmission of noise from on-chip static logic gates through the substrate to the analog circuitry, at the expense of valuable silicon area and, in some cases, increased circuit complexity.
While the use of other logic families, such as folded source-coupled logic (FSCL) and current-steering logic (CSL), have certain advantages, use of these technologies requires circuit redesign. Further, the advantages associated with the use of other logic families, such as FSCL and CSL, do not outweigh the disadvantage of having to redesign CMOS circuitry.
It is therefore desirable to minimize/eliminate the generation of digital switching noise produced by CMOS logic circuits in mixed mode integrated circuits. It is also desirable to retain common CMOS circuit topologies to simplify useage in mixed-mode integrated circuits.